1. Field of the Invention
The present invention generally relates to diversity techniques for reception of diversity signals in a radio receiver, and in particular to a diversity combining method and system where diversity branches are weighted prior to summing them.
2. Description of the Related Art
In general, branch selection diversity and diversity combining are available for reception of diversity signals. With the branch selection diversity, one signal is chosen from the set of diversity branches based on received signal strength. On the other hand, with the diversity combining, especially maximal-ratio combining, the diversity branches are weighted prior to summing them, each weight being proportional to the received branch signal amplitude. In digital mobile communications system such as cellular or cordless telephone systems, there is an increasing tendency to employ the diversity combining technique to provide improved quality of communication services and a wider service area.
There has been proposed a first conventional diversity combiner which is provided with analog-to-digital (A-D) converters for converting the intermediate-frequency (IF) diversity signals to digital diversity signals, respectively. After the respective digital signals are stored onto registers, the stored signals are read in phase with each other to be combined and decoded.
A second conventional diversity combiner has been proposed in Japanese Patent Unexamined Publication No. 7-307724. According to this diversity combining method, for each of the diversity branches, sampled phase data in symbols and a received signal strength indicator (RSSI) level are used to obtain a vector in the I-Q rectangular coordinate system. And the respective obtained vectors for the diversity branches are combined into an output signal. More specifically, the diversity combiner is provided with a first memory for the I component and a second memory for the Q component. The first memory is used to obtain the I component: (RSSI).sup.2 cos (.theta.), and the second memory is used to obtain the Q component: (RSSI).sup.2 sin (.theta.), where .theta. is the sampled phase data.
There are other related documents: Japanese Patent Unexamined Publication Nos. 6-97920 and 7-50627. In the former, by separately detecting a phase modulation component and an amplitude modulation component from each diversity branch signal, a limiter amplifier can be used for the phase modulation detection and further a variation of an received signal strength can be detected from the amplitude modulation component. In the latter, to correct phase variations among branches in N-PSK signal detection, a signal of a first branch is phase-shifted by 2.pi. k/N (k=0, 1, . . . , N-1) with reference to a second branch for each symbol timing to produce N signals. Assuming that the amount of phase variation between two consecutive symbols for each branch is not varied, a signal having the minimum distance of signal points between two consecutive symbols is selected from the N signals, and the selected signal is assumed to be in phase with the first branch.
In the first conventional combiner, however, it is necessary to use a sample clock whose frequency is sufficiently higher than the symbol rate (at least eight times the symbol rate) to adjust the phase with precision. In the case of the digital cellular telephone system having a transmission rate of 42 Kbps, a sample clock of at least 168 KHz is needed. In the case of digital cordless telephone system having a transmission rate of 384 Kbps, a higher sample clock of 1.536 MHz is needed. Therefore, the first conventional system needs expensive A-D converters or a digital signal processor (DSP), especially in the case of high bit-rate system.
In the second conventional combiner, the larger the phase and RSSI resolution, the larger the amount of memory needed in the first and second memories. Assuming 8-bit phase angle data, 8-bit RSSI data, and 8-bit data in rectangular coordinates, there are needed two random access memories (RAMs) each having a capacity of 65,536 words.times.8 bits. To reduce error, increased precision of data in bits is needed, resulting in a larger amount of memory. Such a large amount of memory cannot be built in a single gate array. Therefore, external circuitry is required.